A semiconductor memory device, such as a DRAM device, can consist of a memory cell region in which unit cells for storing information are arranged as an array, and a peripheral circuit region for driving the unit cells. Each unit cell in the memory cell region may include a capacitor and an access transistor, and the capacitor includes a storage electrode, a dielectric layer, and a plate electrode. To increase the capacitance of the thus-constituted capacitor, a cylindrical structure or a stack structure using a dielectric layer of a high dielectric constant are widely employed. By forming such a capacitor in the memory cell region, a step is typically formed at the boundary between the peripheral circuit region and the memory cell region. Since the pattern density of the memory cell region is higher than that of the peripheral circuit region, the patterns in the edge and center of the memory cell region are formed with different bias from each other due to the proximity effect in photolithography processes. Thus, photolithography process margins are typically reduced in the memory cell region.
To solve the above discrepancy, a method has recently been suggested in which at least one dummy column is disposed at the edge of a memory cell region. In this method, the difference between the sizes of patterns formed in the center and edge of the memory cell region can be further reduced. Here, the dummy column has a corresponding dummy bit line coupled thereto.
FIG. 1 is a layout view of the edge portion of a conventional memory cell region in an exemplary DRAM memory device. Referring to FIG. 1, the conventional memory cell of the DRAM device includes a plurality of cell active regions 24, 25, 35, 36, 44, and 45 arranged in a zigzag pattern, a plurality of word lines 11, 12, 13, 14, 15 and 16 arranged so that a pair of word lines cross over each active region, drain regions each defined in an active region between a pair of word lines, a pair of source regions defined by active regions adjacent to the drain regions with a pair of word lines intervening between the source regions, a plurality of storage electrode contact holes 61, 62, 63, 71, 72, 73, 81, 82, and 83 for exposing the source regions, a plurality of storage electrodes 21, 22, 23, 31, 32, 33, 41, 42, and 43 connected to the source regions via respective storage electrode contacts, plate electrodes 90 which expose the drain regions, a plurality of bit line contacts 64, 65, 75, 84, and 85 for contacting a predetermined area of each drain region, and a plurality of bit lines 51, 52, and 53 covering the bit line contacts and disposed in a perpendicular direction relative to the plurality of word lines. Here, the bit line 51 disposed at the outermost edge of the memory cell region serves as a dummy bit line, and the bit lines 52 and 53 adjacent to the dummy bit line 51 serve as actual bit lines for transferring information. Here, as will be understood by those skilled in the art, a ground potential or a power voltage is generally applied to the dummy bit line 51.
When a DRAM cell is formed using a mask fabricated by the above layout, a stringer S (i.e., electrical "short") may form between adjacent storage electrodes. As shown in FIG. 1, when the stringer S is produced between a storage electrode of a dummy cell (e.g., storage electrode 21) which is connected to the dummy bit line 51, and a storage electrode of an actual cell adjacent to the dummy cell (e.g., the storage electrode 31), the DRAM device may malfunction. For example, when a power voltage is applied to both the bit line 52 and the word line 12 to store information corresponding to logic "1" in the storage electrode 31, a portion of the semiconductor channel region where the active region 35 and the word line 12 intersect is inverted and the power voltage is transferred to the storage electrode 31. Here, in the event the dummy bit line 51 is set at ground potential and the word line 11 is not selected, the storage electrode 21 is electrically isolated from the dummy bit line 51. Thus, the storage electrode 21 has the same potential as that of the storage electrode 31, that is, the power voltage (i.e., logic "1").
However, when the power voltage is applied to the word line 11 to store predetermined information in the storage electrode 41 or to read out the information stored in the storage electrode 41, a channel is formed at the portion where the word line 11 and an active region 24 intersect. When this occurs, the storage electrode 21 becomes electrically connected to the grounded bit line 51, and thus the storage electrode 21 is "pulled" to the ground potential. In addition, since the storage electrode 31 is also connected to the storage electrode 21 via the stringer S, information stored in the storage electrode 31 of an actual memory cell, that is the information corresponding to the logic "1", vanishes. Therefore, when the information stored in the storage electrode 31 is read, unintended information is accessed and an operational failure occurs.
Alternatively, in the event a power voltage (i.e., logic "1") is applied to the dummy bit line 51, when information corresponding to logic "0" is stored in the storage electrode 31 and the information of the storage electrode 31 is read, incorrect information corresponding to the logic "1" will be read.
Thus, although the conventional DRAM device can reduce pattern failures generated at the edge of a memory cell region by providing a dummy bit line, it typically cannot overcome operation failures caused by a stringer remaining between storage electrodes.